Example embodiments relate to address scheduling methods for three-dimensional (3D) memory cell arrays, and more particularly, to address scheduling methods for 3D memory cell arrays in non-volatile memory devices including a plurality of multi-level cells.
Flash memory used as electrically erasable programmable read-only memory (EEPROM) may have an advantage of random access memory (RAM) in which data can be readily programmed and erased and an advantage of ROM in which data can be retained without supply of power.
Flash memory is usually divided into NAND flash memory and NOR flash memory. NOR flash memory may have a structure in which memory cells are independently connected to a bit line and a word line, thereby having an excellent random access time characteristic. On the other hand, NAND flash memory may be improved in terms of the degree of integration because of its structure in which a plurality of memory cells may be connected to one another, thereby requiring only one contact per cell string. Accordingly, the NAND structure is usually used in highly integrated flash memory.
Multi-bit cells which may be capable of storing plural data in a single memory cell. This type of a memory cell is generally called a multi-level cell (MLC). On the other hand, a memory cell capable of storing a single bit is called a single level cell (SLC).
There may occur a coupling effect between memory cells connected to adjacent word lines when a program operation is performed according to conventional address scheduling methods. To compensate for the coupling effect, a program bias voltage may be applied to two adjacent word lines alternately when a 2-bit MLC is programmed. These address scheduling methods, however, may deteriorate device operating speed.